1. Field of the Invention
The present invention relates to a solid state imaging device, an imaging apparatus, an electronic apparatus, an AD converter, and an AD conversion method.
2. Description of the Related Art
Semiconductor devices for detection of physical quantity distribution in which a plurality of unit elements (for example, pixels) sensitive to electromagnetic waves input from the outside, such as light or radiant rays, are arrayed linearly or in a matrix are used in various fields.
For example, in a field of visual equipment, CCD (Charge Coupled Device) type, MOS (Metal Oxide Semiconductor) type, or CMOS (Complementary Metal Oxide Semiconductor) type solid state imaging devices that detect light (an example of an electromagnetic wave) among the physical quantities are used. These solid state imaging devices read the physical quantity distribution, which has been converted into an electrical signal by unit elements (in a solid state imaging device, pixels), as an electrical signal.
For example, in an X-Y address type solid state imaging device, a plurality of pixel transistors are arrayed in a two-dimensional matrix in order to form a pixel section. In addition, accumulation of signal charges corresponding to incident light is started for every line (row) or every pixel and signals having a current or a voltage based on the accumulated signal charges are read sequentially from each pixel by address designation. Here, in the MOS type solid state imaging device (including the CMOS type solid state imaging device), a column read method (column parallel output method) of reading pixel signals in a row unit from a pixel section by accessing one row simultaneously is often used as an example of address control. The analog pixel signal read from the pixel section is converted into digital data, if necessary, by an analog digital converter (ADC). Accordingly, various methods for AD conversion have been proposed.
As an AD conversion method, various methods may be considered from points of view of circuit structure, processing speed (improvement in the speed), resolution, and the like. As an example, there is a reference signal comparing type AD conversion method (see JP-A-2005-328135). In addition, the reference signal comparing type is also called a slope integration type or a ramp signal comparing type. In the reference signal comparing type. AD conversion method, a so-called ramp shaped reference signal (ramp wave: a wave with predetermined amplitude and inclination; also called a staircase wave) whose level changes gradually is used for voltage comparison for conversion into digital data. Moreover, an analog unit signal and the reference signal are compared with each other, and digital data of the unit signal is acquired on the basis of the count value obtained by performing count processing in a count operation effective period based on the comparison processing result. Using a method (called a column AD method) in which the reference signal comparing type AD conversion method and the column read method are combined, an analog output from a pixel can be AD-converted in column parallel in a low frequency region. This is suitable for an image sensor in which high definition and high speed are requested to be compatible.
In recent years, CMOS sensors are widely mounted in mobile phones, digital cameras (compact type or high-class single-lens reflex type), camcorders, surveillance cameras, guiding apparatuses, and the like due to advantages of low power consumption or high speed. Moreover, high-performance and high-definition CMOS sensors in which functional circuit blocks for image processing and the like are provided together on a chip have also appeared in recent years. It may be considered to apply the reference signal comparing type AD conversion method to those described above.
FIG. 9A is a view showing the structure disclosed in JP-A-2005-328135. Here, the configuration example of a solid state imaging device 1Z to which the reference signal comparing type AD conversion method disclosed in JP-A-2005-328135 is applied is shown after simple change. The solid state imaging device 1Z includes a pixel array section 10, a horizontal scanning section 12, a vertical scanning section 14, a PLL circuit 20x, a system control unit 20y which controls the entire system, a column AD conversion section 26, a reference signal generating section 27 which generates a reference signal SLP_ADC, a sense amplifier 28a, and a signal processing and interface section 28z. In the pixel array section 10, unit pixels 3 are arrayed in a two-dimensional matrix. The PLL circuit 20x generates an internal clock CKX on the basis of a basic clock CK input from the outside and supplies the internal clock CKX to the reference signal generating section 27 or a counter section 254.
The column AD conversion section 26 has a comparing section 252 and a counter section 254 for every vertical column. As an example, the counter section 254 is a ripple counter, in which latches LT_00 to LT_12 provided in 13 stages are connected in series to each other, and has a 13-bit-correspondence configuration in which the latches are connected such that switching between an up count and a down count is possible.
Data D0 to D12 output from the counter section 254 has a small amplitude level (for example, several 100 mVp-p) and are transmitted to the sense amplifier 28a through the horizontal signal line 18. The sense amplifier 28a amplifies the data D0 TO D12 with a small amplitude level up to a logic level (for example, 2 to 3 Vp-p) and then transmits them to the signal processing and interface section 28z. The signal processing and interface section 28z performs predetermined digital signal processing on the 13-bit data D0 TO D12 and transmits them to a subsequent-stage circuit (not shown) as 12-bit output data Dout (D0 to D11).
The AD conversion operation is as follows. First, a pixel signal voltage Vx is read from the unit pixel 3 toward the column AD conversion section 26 through the vertical signal line 19. The comparing section 252 compares the pixel signal voltage Vx with the reference signal SLP_ADC from the reference signal generating section 27 and supplies the comparison result to the latch LT_00 provided in the first stage of the counter section 254. The internal clock CKX is also supplied from the PLL circuit 20x to the latch LT_00. For example, when the comparison result of the counter section 254 is H, the counter section 254 performs a count operation. AD conversion is realized by acquiring the count result as digital data of the pixel signal voltage Vx. That is, an AD converter is provided for every vertical column, the pixel signal voltage Vx (analog signal) of each unit pixel 3 in the selected row is collectively read to each vertical signal line 19, and each of a reset level and a signal level of the pixel signal voltage Vx is directly AD-converted.
In the technique disclosed in JP-A-2005-328135, differential processing of AD conversion results of the reset level and the signal level is also performed simultaneously during the AD conversion processing. This is to perform CDS (Correlated Double Sampling) processing in a digital region by performing the reference signal comparing type AD conversion processing for every vertical column. In this case, since a disadvantage when performing the CDS processing in an analog region is eliminated, highly precise noise removal can be executed. In the column AD method, parallel processing is performed for every row in the horizontal direction of a screen. Accordingly, it is not necessary to perform high-frequency driving for horizontal scanning and the AD conversion is performed only with a low-speed scanning frequency in the vertical direction. This is advantageous in that a noise component and a signal component generated in a high frequency region can be easily separated from each other.
FIG. 9B is a view showing the structure disclosed in JP-A-56-096527. In the technique disclosed in JP-A-56-096527, AD conversion is performed by setting the inclination of a reference signal high before the value reaches the neighborhood of the target value and the result is held, and the AD conversion is performed by changing the inclination to be low after reaching the target value. For such a change of the reference signal, a relatively large (understood as such from the drawing) reference voltage source and logic control circuit are necessary.
FIG. 9C is a view showing the structure disclosed in JP-A-2002-232291. In first processing, a pixel signal is applied to one input terminal of a comparator provided for each column and a staircase wave of a large voltage step is applied to the other input terminal by a reference voltage. The count value corresponding to the number of steps when a signal of the comparator is inverted is held in a latch circuit as an upper bit, and the reference voltage at that time is held in a capacitor. The capacitor is an example of a reference voltage holding means for holding a reference voltage when a comparison result of a comparing means changes. In second processing, a small voltage step is applied through another capacitor by the reference voltage, and the count value when a signal of the comparator is inverted is held again in a latch circuit for lower bits. That is, in the second processing, AD conversion is performed by changing the reference voltage in the shape of a staircase wave in a step corresponding to a lower data bit region with the value of the reference voltage held in the reference voltage holding means (capacitor) as a starting point. This is a method in which a change point of the inclination of the reference voltage is different for every pixel.
FIG. 9D is a view showing the structure disclosed in U.S. Pat. No. 6,670,904. Two kinds of reference signals are used, and a process of conversion from analog to digital is performed through two divided steps of “coarse” and “fine” in order to shorten the conversion cycle time from analog to digital. A configuration is adopted in which a reference signal for “coarse” is input to a comparator 306 through a switch 304 and a reference signal for “fine” is input to the comparator 306 through a capacitor 302. As a preferable mode, the reference signal for “coarse” is made to correspond to a most significant bit (MSB) and the reference signal for “fine” is made to correspond to a least significant bit (LSB). Moreover, in first processing, the switch 304 is turned on to perform comparison with an analog signal using only the reference signal for “coarse”. When the comparator 306 detects that the reference signal and the analog signal have become equal, the switch 304 is turned off using the information and the counter value at this time is held. Then, second AD conversion processing is performed by superimposing the reference signal for “fine” on the value (held in the capacitor 302) of the reference signal for “coarse” at the time. Similar to the method disclosed in JP-A-2002-232291, this is a method in which a change point of the inclination of the reference voltage is different for every pixel.